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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
DESCRIPTION
The SC1109 was designed for the latest high speed motherboards. It combines a synchronous voltage mode controller (switching section) with two low-dropout linear regulator controllers. The voltage mode controller provides the power supply for the system AGTL bus. The 1.8V and 2.5V linear controllers power the Chipset and clock circuitry. The SC1109 switching section features lossless current sensing and latched driver outputs for enhanced noise immunity. It operates at a fixed frequency of 200kHz, the output voltage is internally fixed at 1.2V The SC1109 linear sections are low dropout regulators designed to track the 3.3V power supply when it turns on or off.
FEATURES * * * * * * * *
1.8V, 2.5V linear controllers LDOs track input voltage within 200mV until regulation Integrated drivers Power Good Signal Soft Start Lossless Current Sense
APPLICATIONS
Pentium III Motherboards Triple power supplies
(R)
ORDERING INFORMATION
Part Number
(1)
Package
Linear Voltage
Temp. Range (TJ)
SC1109CSTR SC1109EVB
SO-16
1.8V/2.5V 0 to 125C Evaluation Board
TYPICAL APPLICATION CIRCUIT
12V IN 5V STBY 5V IN C2 2x1500uF C3 0.1uF 11 C5 0.1uF 4 C6 0.1uF 5 14 POWER GOOD C9 0.1uF 12 13 15 16
Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices.
C1 0.1uF C4 0.1uF 3 10 9 7 Q2 C7 3x1500uF R1 2.2 Q1 L1 4uH
1.2V 6A
+
U4 VCC BCAP+
SC1109CS STBY BST DH
BCAPSS/EN PWRGD VOSENSE GATE2 LDOS2
PHASE
VTT 8 6 2 1 R2 2.2 + C8 0.1uF
DL GND GATE1 LDOS1
3.3V IN Q3 + C10 330uF 2.5V + C11 330uF + C12 330uF 1.8V Q4
Pentium is a registered trademark of Intel Corporation
1
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TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
ABSOLUTE MAXIMUM RATINGS
Parameter VCC to GND STBY to GND BST to GND PHASE to GND LDOSx Operating Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 seconds Thermal Impedance Junction to Ambient Thermal Impedance Junction to Case Symbol Maximum -0.3 to +7 -0.3 to +7 -0.3 to +15 -1 to +8 -0.3 to 5 0 to +70 0 to +125 -65 to +150 300 130 30 Units V V V V V C C C C C/W C/W
TA TJ TSTG TL JA JC
Note: Exceeding the Absolute Maximum Ratings may cause irreversible damage to the device.
ELECTRICAL CHARACTERISTICS
Unless specified: VOSENSE = VO; Vcc=4.75V to 5.25V; STBY=4.75V to 5.25V; BST = 11.4V to 12.6V; TA = 0 to 70C
PARAMETER Supply (VCC) Supply Voltage Supply Quiescent current Supply Operating current Switching Section Output Voltage(1) Load Regulation(1) Line Regulation(1) Oscillator Frequency Oscillator Max Duty Cycle Current Limit trip (Vin-VPHASE) Gain (AOL)(3) Under Voltage Lock Out Threashold Hysteresis Power Good Power Good Threshold Voltage Soft Start / Enable SS/EN Source current(2) SS/EN Sink current(2) Shutdown Voltage
SYM VCC ICCQ ICC VTT LOADREG LINEREG fOSC D VtripIlimit GAINVTT VCCHIGH VCCHYST PGth
CONDITIONS
MIN 4.4 6
TYP 5 8
MAX 5.25 12 20 1.212
UNITS V mA mA V % % kHz % mV dB V mV
VCC = 5V, SS/EN = 0V VCC = 5V, SS/EN > 1V IO = 2A IO = 0A to 6A Vin=4.75V to 5.25V
1.188
175 90 180 VOSENSE to VO
1.200 1 0.15 200 95 200 35 4.2 200
225 220
88 10 2 600
112
% A A mV
IsourceSS/EN VSS/EN = 0V to 3.5V IsinkSS/EN VSS/EN = 0V to 3.5V VSS/EN
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
ELECTRICAL CHARACTERISTICS (Cont.)
Unless specified: VOSENSE = VO; Vcc=4.75V to 5.25V; STBY=4.75V to 5.25V; BST = 11.4V to 12.6V; TA = 0 to 70C
PARAMETER Internal Drivers Peak DH Source Current Peak DH Sink Current Peak DL Source Current Peak DL Sink Current Dead time Linear Sections Standby Voltage Standby Quiescent current Tracking Difference
(4)
SYM IsourceDH IsinkDH IsourceDL IsinkDL TDEAD VSTBY ISTDBYQ DeltaTRACK VLDO1 VLDO2 LOADREG LINEREG ZOUT ZIN GAINLDO VgateLDO1 VgateLDO2
CONDITIONS BST-DH = 4.5V DH-GND = 3.1V DH-GND = 1.5V VCC-DL = 4.5V DL-GND = 3.1V DL-GND = 1.5V
MIN 500 500 100 500 500 100 40 4.4
TYP
MAX
UNITS mA mA mA mA mA mA ns
100 5 200 5.25 5
V mA mV V V % %
VSTBY = 5V, SS/EN = 0V IO = 0 to 4A, 3.3V Vin = 3.3V IO = 0 to 4A, 3.3V Vin = 3.3V IO = 0 to 4A, 3.3V Vin = 3.3V 3.3V Vin = 3.13V to 3.47V, Io VGATE(1,2) = 6.5V 10 LDOS (1,2) to GATE (1,2) VSTDBY = 5V VSTDBY = 5V 50 8 7
Output Voltage LDO1 Output Voltage LDO2 Load Regulation Line Regulation LDOS(1,2) Output Impedance LDOS(1,2) Input Impedance Gain (AOL)
(3)
1.782 1.818 1.854 2.475 2.525 2.575 0.3 0.3 1 1.5
k k dB V V
LDO1 Gate Voltage LDO2 Gate Voltage
Notes: (1) All electrical characteristics are for the application circuit on page 6. (2) Soft start function is performed after Vcc is above the UVLO and SS/EN is above 600mV. The Soft start capacitor is then charged at a 10uA constant current until SS/EN is charged to above 1V. (3) Guaranteed by design (4) Tracking Difference is defined as the delta between 3.3V Vin and the LDO1, LDO2 output voltages during the linear ramp up until regulation is achieved.
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
PIN DESCRIPTION
Pin 1 2 3 Pin Name LDOS1 GATE1 STBY Pin Function Sense Input for LDO1 Gate Drive Output LDO1 (1.8V) 5V Standby Input, supplies power for Ref, Charge Pump, Oscillator and FET controllers. Positive Connection to Boost Capacitor Negative Connection to Boost Capacitor Ground Phase Node Low Side Driver Output High Side Driver Output Boost Input Power Supply Input Open Collector Power Good Flag for 1.2V Output Output Sense Input for 1.2V Output Soft Start/ Enable Gate Drive Output LDO2 (2.5V) Sense Input for LDO2
PIN CONFIGURATION
Top View
LDOS1 GATE1 STBY BCAP+ BCAPGND PHASE DL
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
4 5 6 7 8 9 10 11 12 13 14 15 16
BCAP+ BCAPGND PHASE DL DH BST VCC PWRGD VOSENSE SS/EN GATE2 LDOS2
LDOS2 GATE2 SS/EN VOSENSE PWRGD VCC BST DH
(16 Pin SOIC)
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
BLOCK DIAGRAM
VCC
VBG
1.2V Bandgap UVLO 200mV
+ -
OVER CURRENT
+ -
-10% +10% HIGH SIDE DRIVE
BST DH PHASE
SHOOT THRU CONTROL
-
PWRGD
+
OSCILLATOR
+
PWM
VCC R Q S
LOW SIDE DRIVE
VOSENSE
VCC VBG
+
ERROR AMP
+
SET DOMINATES
DL GND
S
10uA 0.8V
Q + R HICCUP LATCH FAULT LOW SIDE OFF
SS/EN
SS/EN
0.6V
+ -
5VSTBY
2uA
5VSTBY
VBG
+ -
GATE2 LDOS2
5VSTBY
5VSTBY
CHARGE PUMP
STBY
OSCILLATOR
VBG
+ -
GATE1 LDOS1
BCAP+
BCAP-
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
APPLICATION CIRCUIT
12V IN GND
J1 J2
5V STBY J3 GND 5V IN J4 J5 C2 + R1 10k 1500uF C5 + 1500uF GND J8 GND J10 POWER GOOD J11 C13 0.1uF C12 0.1uF C7 0.1uF 5 14 12 13 15 16 C3 0.1uF R5 0 U1 11 C6 0.1uF 4 VCC BCAP+ SC1109CS STBY BST DH BCAPSS/EN PWRGD VOSENSE GATE2 LDOS2 DL GND GATE1 LDOS1 8 D1N4148 6 2 1 PHASE 3 10 9 7 D1 R3 0 Q2 C8 IRLR3103 + C9 + C10 + 1500uF 1500uF 1500uF GND J12 J13 GND R2 0 R4 2.2 Q1 IRLR3103 L1 4uH
1.2V 6A
C1 0.1uF C4 0.1uF
5V IN J6
VTT J7 J9 C11 0.1uF VTT
3.3V IN J14 Q3 IRLR3103 2.5V J15 + GND J17 C14 330uF GND J18 + C15 330uF GND J19 Q4 IRLR3103 1.8V J16
+
C13 330uF
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
MATERIALS LIST
SC1109 Evaluation board Revised: Friday, August 11, 2000 SC1109EVB Revision: 1.1 Bill Of Materials August 8,2000 13:17:55 Page1 Item Quantity Reference Part 1 7 C1,C3,C4,C6,C7,C11,C12,C13 0.1uF 2 5 C2,C5,C8,C9,C10 1500uF 3 3 C13,C14,C15 330uF 4 1 D1 D1N4148 5 1 J1 12V IN J2,J4,J8,J10,J12,J13,J17, 6 9 GND J18,J19 7 1 J3 5V STBY 8 2 J5,J6 5V IN 9 2 J7,J9 VTT 10 1 J11 POWER GOOD 11 1 J14 3.3V IN 12 1 J15 2.5V 13 1 J16 1.8V 14 1 L1 4uH 15 4 Q1,Q2,Q3,Q4 IRLR3103 16 1 R1 10k 17 2 R2,R3 0 18 1 R4 2.2 19 1 R5 0 20 1 U1 SC1109CS
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109 (VTT) Eff. vs Iout (Vin = 5.0V) 90.0% 80.0% 70.0%
SC1109
SC1109 (VT T ) L ine Reg. vs Vin (Iout = 6.0A)
0.350% 0.300% Line Reg.(%)
IRL3103R(V1.8,V2.5 No load)
Efficiency(%)
60.0% 50.0% 40.0% 30.0% 20.0% 10.0% 0.0% 0.00 2.00 4.00 Iout_Vtt (Amps) 6.00 8.00
0.250% 0.200% 0.150% 0.100% 0.050% 0.000% 4.000 4.500 5.000 5.500
Vin (V)
IRL3103R(V1.8,V2.5 No load)
6.000
6.500
7.000
Typical VTT Efficiency at Vin=5V
SC1109 (VTT) Load Reg. vs Iout (Vin = 5.0V) 0.000% -0.100%
Typical VTT Line Regulation at Iout = 6 Amps
S C 1 1 0 9 ( V T T ) L i n e R e g . v s V in (Iout = 3.0A) 0.120% 0.100%
IRL3103R(V1.8,V2.5 No load)
Load Reg.(%)
Line Reg.(%)
IRL3103R(V1.8,V2.5 No load)
-0.200% -0.300% -0.400% -0.500% -0.600% 0.00 2.00 4.00 Iout_Vtt (Amps) 6.00 8.00
0.080% 0.060% 0.040% 0.020% 0.000% 4.700 4.800 4.900 5.000 V in (V) 5.100 5.200 5.300
Typical VTT Load Regulation at Vin=5V
Typical VTT Line Regulation at Iout = 3 Amps
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
SC1109 Gain & Phase Margin
50 200
180 40 160 30
Gain
140
Phase Margin (Deg.)
Gain (dB)
20
120
10
Phase Margin
100
80 0 60 -10 40
-20 10 100 1,000 frequency(Hz) 10,000
20 100,000
Typical VTT Gain/Phase plot at Vin=5V Iout = 3 A
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
THEORY OF OPERATION
The SC1109 has integrated a synchronous buck controller and two Low drop out regulator controllers into a 16 Pin SOIC package. The switching regulator provides a 1.2V (VTT) bus termination voltage for use in AGTL (Assisted Gunning Transceiver Logic), while the dual LDO regulators provide 1.8V, and 2.5V to power up the Chipset and the Clock circuitry used in Pentium(R) III Motherboards. tors voltage reaches 1V, when the error amplifier output starts to cross the oscillator triangular ramp of 1V to 2V. As the SS/EN pin continues to rise, the error amplifier output also rises at the same rate and the duty cycle increases. Once the VTT output has reached regulation and is within 1.2V 12% , an open collector power good flag is activated, and the error amplifier output will no longer be clamped to the SS/EN voltage and will stay between 1V to 2V and maintain regulation of 1%. The SS/EN voltage continues to rise up to 2.5V and will stay at that voltage level during normal operation.
Vcc
SUPPLIES
Two supplies, VSTBY, and VCC are used to power the SC1109. VSTBY supply provides the bias for the Internal Reference, Oscillator, and the LDO FET controllers. The VCC supply provides the bias for the Power Good circuitry, and the high side FET Rdson sensing/over current circuitry, VCC also is used to drive the low side Mosfet gate. An external 12V supply or a classical boot strapping technique can provide the gate drive for the upper Mosfet.
PWM CONTROLLER
SC1109 is a voltage mode buck controller that utilizes an internally compensated high bandwidth error amplifier to sense the VTT output voltage. External compensation components are not needed and a stable closed loop responce is insured due to the internal compensation. START UP SEQUENCE Initially during the power up, the SC1109 is in under voltage lock out condition. The latch (SET dominant) in the hiccup section is set , and the SS/EN pin is pulled low by the 2uA soft start current source. Mean while the high side and low side gate drivers DH, and DL are kept low. Once the VCC exceeds the UVLO threshold of 4.2V, the latch is reset and the external soft start capacitor starts to be charged by a 10uA current source. The gate drives are still kept off until the soft start capacitors voltage rises above 600mV, when the low side gate is turned on , and the high side gate is kept off. The gate drive status stays the same until the capaci-
PowerGood
Softstart
PhaseNode
If an over current condition occurs, the SS/EN pin will discharge by a 2uA current source, from 2.5V to 800mV. During this time both DH, and DL will be turned off. Once the SS/EN reaches 800mV, the low side gate will be turned on, and the SS/EN pin will again start to be charged by the 10uA current source, and the same soft start sequence mentioned above will be repeated.
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
OVER CURRENT
Upper Mosfet's Rdson is used to monitor the drop across the top FET due to an over current condition. This Method of current sensing minimizes any unnecessary losses due to external sense resistance. An internal comparator with a 200mV reference monitors the Drop across the upper FET, Once the Vdson of the Mosfet exceeds the 200mV limit, the low side gate is turned on and the upper FET is turned off. Also an internal latch is set and the Soft start capacitor is discharged. Once the lower threshold of the soft start circuit is crossed, the same Softstart sequence mentioned previously is repeated. This sequence is repeated until the over condition is removed.
Upper Gate
Mosfet gate drive can be provided by an external 12V supply that is connected from BST to GND. The actual gate to source voltage of the upper Mosfet will approximately equal 7V (12V-VCC). If the external 12V supply is not available, a classical boot strap technique can be implemented from the VCC supply. A boot strap capacitor is connected from BST to Phase while VCC is connected through a diode (Schottky or other fast low VF diode) to the BST. This will provide a gate to source voltage approximately to VCC-Vdiode drop.
Lower Gate
Lower Gate
PhaseNode
Lower Gate
PhaseNode
Vtt Shorted
Shoot through control circuitry provides a 100ns dead time to ensure both upper and lower MOSFET will not turn on simultaneously and cause a shoot through condition.
Upper Gate Lower Gate
GATE DRIVERS
The Low side gate driver is supplied from VCC and provide a peak source/sink current of and 500mA. The high side gate drive is also capable of sourcing and sinking peak currents of 500mA. The high side
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
DUAL LDO CONTROLLERS
SC1109 also provides two low drop out linear regulator controllers that can be used to generate a 1.8V (LDO2) and 2.5V (LDO1) outputs. The LDO output voltage is achieved by controlling the voltage drop across an external Mosfet from a 3.3V supply voltage. The output voltage is sensed at the LDOS pin of the SC1109 and compared to an internal reference. The gate drive to the external Mosfet is then adjusted until regulation is achieved. In order to have sufficient voltage to the gate drives of the external Mosfet, an internal charge pump is utilized to boost the gate drive voltage to about two times the VSTBY. The internal charge pump charges an external Bucket capacitor to VSTBY and then connects it in series with VSTBY to the LDOs supply at a frequency of about 200kHz. This ensures sufficient gate drive voltage for the LDOs independent of the VCC or the 12V external supply being available due to start up timing sequence from the silver box.
3.3V Vin 2.5V Vout
1.8V Vout
The LDO1, and LDO2 output voltages are forced to track the 3.3V input supply. This feature ensures that during the start up application of the 3.3V, the 1.8V, and 2.5V outputs track the 3.3V within 200mV typical until regulation is achieved. However, the VSTBY should be established at least 500us, to allow the charge pump to reach its maximum voltage, before the linear section will track within 200mV. This tracking will sequence the correct start up timing for the external Chipset and Clock circuitry.
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary for successful implementation of the SC1109 PWM controller. High currents switching at 200kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom FET ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept
as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically "cleaner" grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. Also keep the Phase connection to the IC short, top FET gate charge currents flow in this trace. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load cur-
12V IN 5V STBY 5V IN
U4 VCC BCAP+
SC1109CS STBY BST DH +
BCAPSS/EN PWRGD VOSENSE GATE2 LDOS2
PHASE
VTT
DL GND GATE1 LDOS1
+
3.3V IN
Heavy Lines indicate high current paths.
2.5V + C10 330uF + + 1.8V
Layout diagram for the SC1109
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000 rents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC1109 is best placed over a quiet ground plane area, avoid pulse currents in the Cin, Q1, Q2 loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the output capacitor(s). If this is not possible, the GND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should GND be returned to a ground inside the Cin, Q1, Q2 loop. 6) BST for the SC1109 should be supplied from the 12V supply, the BST pin should be decoupled directly to GND by a 0.1F ceramic capacitor, trace lengths should be as short as possible. If a 12V supply is not
SC1109
available, a classical boot strap method could be implemented to achieve the upper Mosfet's gate drive. 7) The Phase connection should be short . 8) Ideally, the grounds for the two LDO sections should be returned to the ground side of (one of) the output capacitor(s).
5V
+
Vout +
Currents in various parts of the power section
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
COMPONENT SELECTION
SWITCHING SECTION OUTPUT CAPACITORS - Selection begins with the most critical component. Because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. Output capacitor ESR is therefore one of the most important criteria. The maximum ESR can be simply calculated from:
fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from:
V RESR t It Where Vt = Maximumtransient voltage excursion It = Transient current step
For example, to meet a 100mV transient limit with a 10A load step, the output capacitor ESR must be less than 10m. To meet this kind of ESR level, there are three available capacitor technologies.
Each Capacitor Technology Low ESR Tantalum OS-CON Low ESR Aluminum C (F) 330 330 1500 ESR (m) 60 25 44 Qty. Rqd. 6 3 5 Total C (F) 2000 990 7500 ESR (m) 10 8.3 8.8
ILRIPPLE=
VIN 4L fOSC
Ripple current allowance will define the minimum permitted inductor value. POWER FETS - The FETs are chosen based on several criteria with probably the most important being power dissipation and power handling capability. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses. a) Conduction losses are simply calculated as:
2 PCOND = IO RDS(on)
where = duty cycle VO VIN
b) Switching losses can be estimated by assuming a switching time, if we assume 100ns then:
PSW = IO VIN 10 - 2
The choice of which to use is simply a cost/performance issue, with Low ESR Aluminum being the cheapest, but taking up the most space. INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above. The maximum inductor value may be calculated from:
or more generally,
PSW =
IO VIN ( t r + t f ) fOSC 4
L
R ESR C (VIN - VO ) It
c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be:
PRR = Q RR VIN fOSC
To a first order approximation, it is convenient to only consider conduction losses to determine FET suitability. For a 5V in; 2.8V out at 14.2A requirement, typical FET losses would be:
The calculated maximum inductor value assumes 100% duty cycle, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp
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SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000 Using 1.5X Room temp RDS(ON) to allow for temperature rise. FET type IRL34025 IRL2203 Si4410 RDS(on) (m) PD (W) 15 10.5 20 1.69 1.19 2.26 Package D2PAK D2PAK SO-8
SC1109
INPUT CAPACITORS - since the RMS ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size.
BOTTOM FET - Bottom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it, resulting in low switching losses. Conduction losses for the FET can be determined by:
2 PCOND = IO RDS(on) (1- )
For the example above: FET type IRL34025 IRL2203 Si4410 RDS(on) (m) PD (W) 15 10.5 20 1.33 0.93 1.77 Package D2PAK D2PAK SO-8
Each of the package types has a characteristic thermal impedance, for the TO-220 package, thermal impedance is mostly determined by the heatsink used. For the surface mount packages on double sided FR4, 2 oz printed circuit board material, thermal impedances of 40oC/W for the D2PAK and 80oC/W for the SO-8 are readily achievable. The corresponding temperature rise is detailed below: Temperature rise (oC) FET type IRL34025 IRL2203 Si4410 Top FET 67.6 47.6 180.8 Bottom FET 53.2 37.2 141.6
It is apparent that single SO-8 Si4410 are not adequate for this application, but by using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4.
16 (c) 2000 SEMTECH CORP. TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
SYNCHRONOUS PWM CONTROLLER WITH DUAL LOW DROPOUT REGULATOR CONTROLLERS
PRELIMINARY - October 16, 2000
SC1109
OUTLINE DRAWING SO-16
LAND PATTERN SO-16
ECN 00-817
17 (c) 2000 SEMTECH CORP. TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com

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